Japanese Unexamined Patent Publication No. JP-A-2007-86960 discloses a clock-switching circuit which can switch a clock without generating a hazard and a collapse of duty rate. The clock-switching circuit has: a first synchronizing circuit for synchronizing a clock-select signal by a first clock; a second synchronizing circuit for synchronizing the clock-select signal, which the first synchronizing circuit has synchronized by the first clock, by a second clock; and a clock selecting circuit for outputting a “1” (High level) in synchronization with the clock-select signal, which the first synchronizing circuit has synchronized by the first clock, and for selecting a second clock in synchronization with the clock-select signal, which the second synchronizing circuit has synchronized by the second clock.
Japanese Unexamined Patent Publication No. JP-A-10-154020 discloses a technique for a clock-switching circuit operable to perform switching control in synchronization with a level inversion edge of a clock arising at the clock level inversion of the clock, by which a means for monitoring the level of each clock is provided, and the output-stop control of a clock before switching is performed without waiting for a level inversion edge of the before-switching clock immediately after detection of the before-switching clock staying at a non-valid level.
Japanese Unexamined Patent Publication No. JP-A-2004-166194 discloses a technique for preventing oscillating components of a metastable or a glitch from entering an output signal. According to JP-A-2004-166194, on condition that a new clock signal different from a clock signal under outputting is selected in a select signal, an output signal is held at Low level in synchronization with a falling of the clock signal under outputting. After the level holding, a state signal indicating no selection of all clock signals is output and in response to the state signal, an enable signal for validating the selection of all clock signals is generated to validate the selection of a new input signal by the select signal. The validated new input signal is output in synchronization with its falling. When a state signal indicating the new input signal under selecting is then output, an enable signal is generated for validating the selection of an input signal under selecting based upon the state signal and for invalidating the selection of the other input signal.